Master Thesis Discussion
The discussion of the master's thesis of the student (Zeena Abdullah Hammadi), majoring in (Computer Engineering), was conducted on Sunday, 10/23/20222, in the discussion hall (Hall No. 9) in the Department of Control and Systems Engineering. The thesis title is
“Comparison and Performance Enhancement of a Chaotic Interleaver for the Turbo Encoder Circuit”.
This discussion committee consisted of:
1- Prof. Dr. Moayad Sadiq Krouk / Chairman
2- Asst. Prof. Dr. Muhammad Emad Abdel Sattar / Member
3- Lect. Dr. Amir Musa Thuwaini / Member
4- Lect. Dr. Qusay Fadel Hassan / Member and Supervisor Nowadays,
many communication systems need to send data to each other to share information. The data transmission process seems to have errors due to a variety of factors such as interference, signal, and noise. These errors come from several sources and are called channel errors. Channel coding is used to protect data from these errors by adding certain bits to the bits of the transmitted data. The extra bits are used to detect and repair channel problems on the receiving side. Unfortunately errors in the channel usually occur in a graceful manner, which makes it difficult for the channel coding algorithms to track and correct them. Interleaving is used to scramble the data so that the effect of the error burst is minimized. There are many types of interleaving that show effective performance in correcting 1-D errors, but when a 2-D error type occurs, it is observed that interleaving of the chaotic type is the most efficient. The goal of the thesis is to design a single interleaver circuit that can work with different number of bits. So the system, which is designed, has more than one entry of bits and this is called multi-bit and the system is referred to as multi-standard. The purpose of this system is to build a universal interleaver architecture that works for 8, 16, and 24 bits rather than refactoring three systems. These arrays represent interleaver address index generators. Therefore, rather than having each size individually in its own design, this new design allows the system to easily handle more than one size of the matrix input to the system, which is referred to as a multi-criteria system. Messy interleaving (interleaving and deinterleaver) was generated using MATLAB and Simulink software. Simulink was implemented using the Xilinx ISE 14.7 design suite with MATLAB designing the system in this way. On this occasion, we congratulate the postgraduate student (Zeena Abdullah Hammadi) and we wish her continued success.