The master's thesis of student Nora Nizar Kamal, specialized in Computers engineering, was discussed on Sunday, 19-2-2023 at the Department of Control and Systems Engineering. Her work was entitled:

Low-Density Parity Check Codec Power Reduction using Dynamic Voltage Scheduling

The examining committee consisted of:

1. Dr. Ikhlas Kazem Hamza / Chairman

2. Dr. Ahmed Mazhar Hasan / Member

3. Dr. Ali Majeed Hasan / Member

4. Dr. Qusay Fadhil Hasan / Member and Supervisor

5. Dr. Omar Younis Qasim / Member and Supervisor

The research presented reduces the power consumption of an LDPC encoder using a well-known efficient method of energy reduction called dynamic voltage frequency scheduling (DVFS) which is one of the most powerful power reduction strategies in CMOS circuits. This method was adopted to control and determine the optimal voltage level that enters the encoder, so as to reduce its total power consumption. The proposed system relied on a FLC fuzzy logic controller that calculates the input voltages of the encoder based on frequency values to reduce energy consumption as a coder cost.